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Rosetta remodel on intel Xeon Phi

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Rosetta remodel on intel Xeon Phi

Greetings, I am planning to use Rosetta Remodel very soon, and as I am designing a system to do so, I found myself wondering if I could use the xeon phi coprocessor's cores to increase output. I believe it can be done with mpi, but I am uncertain about that, performance and how difficult the setup would be.
Also, about how many RAM is required per core? I remember that certain steps in remodel protocol require quite an amount of RAM, and the Xeon Phi I am trying to get hands on is 8GB for 60 cores.
Any insights is really appreciated.
Thanks in advance.

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Wed, 2016-09-14 15:35

There has been some effort in the community to get Rosetta to fully use the capabilities of the Xeon Phi, but that isn't ready yet. (Not even for internal development use.)

The main issue, as you indicate, is the memory consumption. At the moment Rosetta needs to be used in a multi-processor fashion, with MPI. While Rosetta should functionally work as an MPI program on the Phi, each process would need a full allotment of memory, which for standard Rosetta runs is at least 500 MB, and probably more like 1 GB+, per process. Therefore, you could only use ~10 CPUs on your Phi before you completely exhausted the memory.

We're working on getting Rosetta to run in a shared-memory, multi-threaded capacity, which should reduce the per-processor memory overhead of runs. (You'd still need 1+ GB of memory per process to run Rosetta, but each process could use multiple CPUs.) But getting to that point will take a bit of effort, and we're still in the middle of working on it.

Wed, 2016-09-14 15:50

"I remember that certain steps in remodel protocol require quite an amount of RAM"

I'm pretty sure it loads in a vall to do fragment selection, so that's "whatever size the vall is in memory" times "number of threads".  

Design is also a traditionally memory-intensive step, but it has built-in tools to reduce its memory footprint.  The linear memory interaction graph (-linmem_ig ) reduces memory usage (and, oddly, usually improves performance) on large design runs.

The MinimalistInteractionGraph appears to not exist in Rosetta3 (I guess it was never ported from 2?) but it would be the lowest-memory but longest-time way to do the design step.

Thu, 2016-09-15 08:24

Thank you, that's very helpful since a coprocessor improves other tasks we are planning to do. Then I will compare the output by using a design protocol in Rosetta 3 and 2 with the coprocessor.

Thu, 2016-09-15 16:36